1. Field of the Disclosure
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to thermal management in 3-D devices.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits which substantially determine the overall performance of these devices, other components, such as capacitors and resistors, and in particular a complex interconnect system or metallization system, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.
Typically, as the number of circuit elements, such as transistors and the like, per unit area may increase in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level may also be increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner-level electrical connection, and vias, providing intra-level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials to reduce the parasitic RC (resistive capacitive) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may be substantially restricted by a metallization system, rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants and the constraints imposed by the material characteristics of sophisticated low-k dielectrics. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Thus, the complexity of semiconductor devices provided in a single semiconductor chip may be restricted by the capabilities of the corresponding metallization system and in particular by the characteristics of sophisticated low-k dielectric materials, since the number of metallization layers may not be arbitrarily increased.
For this reason, it has also been proposed to further enhance the overall density of circuit elements for a given size or area of a respective chip package by stacking two or more individual semiconductor chips, which may be fabricated in an independent manner, however, with a correlated design to provide, in total, a complex system while avoiding many of the problems encountered during the fabrication process for extremely complex semiconductor devices on a single chip. For example, appropriately selected functional units, such as memory areas and the like, may be formed on a single chip in accordance with well-established manufacturing techniques including the fabrication of a corresponding metallization system, while other functional units, such as a fast and powerful logic circuitry, may be formed independently as a separate chip, wherein, however, respective interconnect systems may enable a subsequent stacking and attaching of the individual chips to form an overall functional circuit, which may then be packaged as a single unit. In other cases, power circuitry operated at moderately high voltages and having a high power consumption may be combined with sensitive control circuits, wherein both functional units may be provided in separate chips. Thus, a corresponding three-dimensional configuration may provide increased density of circuit elements and metallization features with respect to a given area of a package, since a significantly larger amount of the available volume in a package may be used by stacking individual semiconductor chips. Although this technique represents a promising approach for enhancing volume packing density and functionality for a given package size for a given technology standard, while avoiding extremely critical manufacturing techniques, for instance in view of stacking a large number of highly critical metallization layers, the heat management of these three-dimensional chip arrangements may be difficult, in particular when high power consuming chips are included, as will be described with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a three-dimensional semiconductor configuration 100 according to a typical conventional architecture. In the example shown, the three-dimensional device 100 comprises a first semiconductor chip 110, which is to be understood as a chip including circuit elements based on a semiconductor material, such as silicon and the like. The first semiconductor chip 110 may comprise a substrate 111, for instance a semiconductor material, such a as a silicon material, or any other appropriate carrier material, such as glass and the like. Furthermore, a device layer 112 may be provided above the substrate 111, which may comprise a plurality of semiconductor-based circuit elements, such as transistors, capacitors, resistors and the like, as is required for obtaining the desired electrical functional behavior of the chip 110. For convenience, any such circuit elements are not shown in FIG. 1. Additionally, the chip 110 may comprise a metallization system 113, which may include one or more metallization layers to establish the electrical connections between the circuit elements in the device layer 112. Moreover, the metallization system 113 may provide an appropriate interconnect structure to enable an electrical connection to a second chip 120 that is attached to the first chip to form a three-dimensional chip configuration, thereby significantly enhancing the volume packing density of circuit elements for a given package volume, as discussed above. For instance, corresponding interconnect structures may be provided in the form of vias 113A, which may extend through the metallization system 113 and may directly connect to the device level 112, if required. Similarly, the second chip 120 may comprise a substrate 121, such as a silicon material or any other appropriate carrier material for forming thereon an appropriate semiconductor material, for instance in the form of silicon, in order to define a device level 122, in and above which corresponding circuit elements may be provided. Furthermore, a metallization system 123 may be provided “above” the device level 122 and may comprise one or more metallization layers for providing the required electrical connections of the circuit elements in the device level 122 and an appropriate contact structure for connecting to the first chip 110. For example, the chips 110 and 120 may comprise appropriate bump structures on the basis of which an electrical connection may be established, thereby also attaching the chip 120 with a chip 110 in a mechanically reliable manner. For this purpose, the metallization system 123 may also comprise appropriate bumps or other contact elements (not shown) in combination with corresponding vias 123A for establishing the chip-to-chip connections. It should be appreciated that attaching the chips 110 and 120 by means of the corresponding metallization systems 113, 123, respectively, may be one of a plurality of possibilities. For example, if the number of chip-to-chip connections is moderately low, the chip 120 may be attached to the chip 110 by means of the substrate 121, wherein corresponding through hole vias may establish the electrical connection from the metallization system 113 to the device layer 122 of the chip 120. On the other hand, the metallization system 123 is then available for connecting to a carrier substrate 130, which may be attached to the chip 120, thereby allowing a moderately complex electrical interconnection system from the chip 120 to the carrier substrate 130, which in turn may provide electrical connection to the periphery (not shown). In still other cases, the substrates 111 and 121 may be attached to each other on the basis of corresponding through hole vias for establishing the required chip-to-chip connections, while the corresponding metallization systems 113 and 123 may be available for connecting to further chips, carrier substrates and the like, when a three-dimensional configuration of increased complexity is required. Furthermore, as shown in FIG. 1, the device 100 may comprise a heat sink 140 that is attached to the carrier substrate 130 and may provide an increased surface area for forced or natural convection of air. In other cases, the heat sink may include sophisticated liquid-based cooling systems or may comprise electrically active cooling systems, such as Peltier elements and the like.
Typically, the semiconductor device 100 as shown in FIG. 1 may be formed on the basis of well-established process techniques including the formation of the chips 110 and 120 by using typical manufacturing techniques of semiconductor devices. That is, the chips 110 and 120 may be formed on dedicated wafers by performing a plurality of manufacturing steps for fabricating circuit elements in the corresponding device levels 112, 122, followed by manufacturing techniques for fabricating the corresponding metallization systems 113 and 123, wherein appropriate process steps are also included to provide the vias 113A, 123A for establishing the chip-to-chip connection in a later manufacturing phase. After completing the basic conductor chips, the corresponding carrier wafers may be separated into single chips, thereby providing a plurality of chips 110 and a plurality of chips 120. Thereafter, the chips 110, 120 may be aligned to each other and may be connected, for instance using an adhesive, a corresponding bump structure including, for instance, a solder material, which may be reflowed to establish an electrical connection and also mechanically adhering the chip 110 to the chip 120. Similarly, the carrier substrate 130 may be attached to the resulting stacked chip configuration and finally the heat sink 140 may be installed. It should be appreciated that the process may involve a plurality of additional well-established packaging techniques, for instance encapsulating the chips 110, 120 after attaching to the carrier substrate 130.
During operation of the device 100 in the stacked configuration, heat is generated, for instance, substantially within the corresponding device levels 112 and 122 due to the operation of the corresponding circuit elements, for instance in the form of transistors, resistors and the like. Depending on the specific configuration, frequently, a chip with moderately high power consumption may be provided within the device 100, wherein a corresponding enhanced thermal connection to the heat sink 140 may be required so that the allowable operating temperature within the device levels 112 and 122 may not be exceeded. Thus, conventionally, it is difficult to provide an efficient heat dissipation for any intermediate chips, in particular if more than two individual chips are provided within the device 100, so that the increase in volume packing density may frequently not be compatible with the available heat dissipation capabilities of conventional stacked chip configurations. Thus, due to the reduced heat dissipation capabilities of the individual chips in the configuration 100, significant constraints with respect to overall complexity and thus power consumption of the corresponding individual chips, as well as for their spatial arrangement within the three-dimensional configuration, may be imposed, thereby reducing overall performance and efficiency of the conventional three-dimensional chip configurations.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.